Logic Synthesis Flow（Opensource Digital IC design）

Name: Logic Synthesis Flow（Opensource Digital IC design）
Author: 中科麒芯

逻辑综合

中科麒芯·v1.0.0最新版

Prepares synthesis constraints, explores compile strategies, generates gate-level netlists, checks timing/area/power QoR, performs netlist QC and prepares synthesis handoff. Supports open-source Yosys flows with Liberty libraries and commercial DC/Fusion/Genus flows.

Opensource Digital IC designQoRSDCSynthesisPolyForm-Noncommercial-1.0.0

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name:chip-design-synthesis

description:Use when preparing synthesis constraints, exploring compile strategies, generating a clean gate-level netlist, checking timing/area/power tradeoffs, running netlist QC or LEC, or deciding synthesis signoff for handoff into STA and physical design. Trigger even if the user only mentions SDC, compile QoR, netlist quality, unmapped cells, or synthesis closure.

license:PolyForm-Noncommercial-1.0.0

metadata:

author:中科麒芯

organization:中科麒芯智能技术（南京）有限公司

homepage:https://www.ickylin.com/

contact:info@ickylin.com

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