全部技能

Generate synthesizable RTL source files from the architecture plan and spec extraction results. Use when the user needs to turn an RTL architecture plan into actual SystemVerilog module files with ports, registers, FSM skeletons, and datapath structure.

Use when the user needs to analyze a design specification (PDF/document) and RTL source to extract verification-relevant information and produce a structured testplan. Covers: spec analysis, FSM extraction, register encoding analysis, and testplan generation. This is the first stage of a UVM verification pipeline -no EDA tools required.

Guides waveform-based debugging when log analysis is insufficient; configures dump settings per tool (VCS/Verdi, Xcelium/Simvision), applies failure-category-specific signal tracing strategies (protocol violation, data mismatch, timeout/deadlock, reset issues), and documents waveform findings with EDA tool invocation records.

Generate testbench code from the spec extraction and architecture plan. The testbench is the spec's independent representative and must NOT depend on RTL implementation details. Use when the user needs a TB wrapper, stimulus driver, checker, and basic self-checking infrastructure.

Use when the user needs to generate a UVM verification environment from spec analysis results. Produces: interfaces, transactions, drivers, monitors, agents, scoreboard, virtual sequencer, environment, sequences, vseq_base, package, base test, and testbench top. Coverage collector is NOT generated here -it is produced by coverage-closure (Stage 7). No EDA compilation in this stage -code generation only.

Plan RTL framework, module partitioning, implementation priorities, and scaffold responsibilities from reviewed front-end design facts. Use when the user needs to move from reviewed spec intent into an implementation-ready RTL architecture.

Analyze datapath, control logic, performance constraints, low-power behavior, and verification-sensitive design intent from a digital front-end specification. Use when the user needs a microarchitecture-facing view before RTL partitioning starts.

Generates UVM test classes and virtual sequences from testplan in priority-batched mode (P0 first, then P1, then P2); implements universal 4-step virtual sequence pattern (configure, stimulate, wait, check); enforces factory registration and objection pairing; annotates testplan with coverage tracking and traceability; limits self-correction loops to 3 rounds per batch.

Plan top-level RTL integration, testbench bring-up, filelist structure, and Makefile organization for a digital front-end project. Use when the user needs to move from module planning into coherent top integration and practical compile or simulation preparation.

Generates SystemVerilog Assertions from spec analysis and FSM analysis using bind construct only (non-invasive to RTL); covers protocol compliance, FSM legality, reset value checks, register access rules, and error flag assertions; uses disable iff for reset-phase exclusion; keeps bind file separate for compile-order control; runs 3-round self-correction with signal/module validation against RTL.

Extract interface, register, parameter, clock/reset, and error-handling facts from a digital front-end specification. Use when the user needs to turn a spec into structured engineering inputs before architecture, RTL, or testbench planning begins.

Detect available EDA tools on the current system and generate a working Makefile for front-end RTL compilation, simulation, and lint. Use when the user needs to set up or switch the build environment before compiling or simulating.

Review extracted specification views for consistency before RTL architecture work begins. Use when the user needs to cross-check interfaces (control and data), registers, parameters, clock/reset, and constraints and decide whether the project is ready, risky, or blocked.

Diagnose compile and simulation failures in a front-end digital design project so the next fix is deliberate instead of blind. Use when the user needs to inspect VCS compile logs, simulation logs, and likely design or environment failure classes before deciding how to repair or escalate.

Three modes — (1) Generate synthesizable Verilog RTL from architecture spec when no RTL exists yet. (2) Review integration contracts and filelist of existing RTL. (3) Apply targeted RTL fixes from verification triage diagnostics. Do NOT use for compilation, simulation, testbench generation, SDC constraints, or lint/CDC checks.

Generates functional covergroups from spec analysis (register config space, FSM state/transition, error injection); parses coverage reports from VCS/Xcelium/Questa; classifies coverage gaps by root cause (missing_scenario, wrong_config, dead_code, sampling_issue, encoding_mismatch); drives iterative coverage-driven test generation with gap-to-stimulus mapping; detects plateaus after 2 consecutive rounds with <1% delta; enforces anti-cheating verification ensuring stimulus corresponds to spec-compliant DUT behavior; limits to 5 closure rounds per gap.

Plan testcase structure, generate testbench and UVM verification infrastructure, and apply incremental fixes for an MCU SoC design. Covers test planning (grouping, priorities, sequence hierarchy), TB code generation (directed tests, UVM agents, checkers), and targeted TB fixes from verification triage. Use when verification goals need to be turned into executable tests and testbench code.

Generate or update the specification and architecture documents for an MCU SoC design. Use when the user needs to define or review memory map, interrupts, clock and reset strategy, module partitioning, and produce spec.md and architecture.md as engineering deliverables for downstream RTL and verification.