Physical Design Flow（Opensource Digital IC design）

Name: Physical Design Flow（Opensource Digital IC design）
Author: 中科麒芯

物理实现

中科麒芯·v1.0.0最新版

Plans and reviews the physical design flow from PDK analysis, floorplan, placement, CTS and routing through timing, power, area optimization and GDS signoff. Supports open-source OpenROAD/KLayout flows as well as commercial Innovus, ICC2 and Calibre-based EDA flows.

DRC/LVSOpensource Digital IC designPhysical-DesignPNRQoRSignoffPolyForm-Noncommercial-1.0.0

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name:chip-design-pd

description:Use when planning or reviewing physical design from floorplan through signoff, including placement, CTS, routing, timing optimization, power optimization, area optimization, and final signoff delivery. Trigger even if the user only mentions congestion, CTS, routing DRC, timing closure, IR/EM, LVS, or GDS signoff.

license:PolyForm-Noncommercial-1.0.0

metadata:

author:中科麒芯

organization:中科麒芯智能技术（南京）有限公司

homepage:https://www.ickylin.com/

contact:info@ickylin.com

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